The combination of industry-leading performance and capacity with the best integrated debug and analysis environment makes ModelSim the simulator of choice for both ASIC and FPGA design.
Combining single kernel simulator (SKS) technology with a unified debug environment for VHDL, Verilog, SystemVerilog, , and SystemC makes ModelSim the world’s most widely used simulator.
The ModelSim product range includes ModelSim PE, LE & SE covering the complete range of requirements from small FPGA design through to the largest System on Chip (SoC) devices.
ModelSim PE (Personal Edition) is the industry-leading, Windows-based simulator for VHDL, Verilog, or mixed-language simulation environments offering a very cost effective solution for RTL and gate level simulation.
ModelSim LE (Linux Edition) is our Linux-based simulator with Dataflow Window and Waveform Compare included for better debug productivity. For applications requiring the Linux platform, LE is the ideal choice. ModelSim LE is currently Verilog only.
ModelSim SE (System Edition) combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems and attain ASIC gate-level sign-off. ModelSim SE offers the ability to simulate very large designs with its support of 32 and 64 bit UNIX and Linux and 32 bit Windows®-based platforms.
ModelSim Additional modules
Waveform Compare
The Waveform Compare feature compares the results of two simulations in order to identify design errors. Waveform Compare is completely configurable offering continuous compares, clocked compares, and even create complex compares using ModelSim's virtual signal capabilities. Waveform Compare results can be viewed in a display window or captured in text files. Included with ModelSim SE & LE. Cost option for PE.
Code Coverage
ModelSim code coverage analysis offers an easy-to-use, integrated code coverage capability that helps develop more complete, robust testbenches quickly. Coverage types supported include statement coverage, branch coverage, condition coverage, branch coverage & finite state machine coverage.
Swift interface
The Swift Interface option for Modelsim PE or ModelSim Designer opens up a part of the VHDL Foreign Language Interface (FLI) to simulate Swift C Models, also known as Logic Modelling SmartModels.
The Swift Interface option is a requirement for fast simulation of the Xilinx RocketIO (gt), Ethernet MAC (emac) orPowerPC (PPC405) cores, which are supplied as Swift "C" Models, for VHDL designs. The Swift format offers vastly greater simulation performance over the instantiation of these cores as gate level netlists.